Toward carrier-scale general-purpose node

In this paper, we elucidate the main performance bottleneck in realizing packet processing which require carrier-scale huge tables to lookup (carrier-scale packet processing) on top of general-purpose servers. Our experimental quantitative analysis using DPDK-Click based packet processing model reveals that performance degradation of the carrier-scale packet processing is mainly caused by increased CPU cache misses with increasing number of input traffic flows. This indicates that the main performance bottleneck of carrier-scale packet processing using general-purpose hardware is the lack of memory response performance. As a solution to the bottleneck, we propose novel server architecture that utilizes Hybrid Memory Cube (HMC), a sort of 3D-stacked DRAM, to reinforce memory response performance in terms of concurrency. Our simulation based evaluation shows that our proposed server architecture can realize more than 40 Gbps carrier-scale packet processing without any dedicated hardware. Our work shows that augmented concurrency of memory response is as important as parallel processing at multi-core CPU to improve the system level performance of carrier-scale packet processing using general-purpose hardware.