"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 /spl mu/m SOI and bulk technology

This paper describes power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines/spl times/64 bitlines) fabricated in 0.25 /spl mu/m Silicon on Insulator (SOI) and bulk technologies. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.5% per 10/spl deg/C reduction in temperature. The standby power for SOI reduces by 1.5% to 3% per 10/spl deg/C temperature drop down to -30/spl deg/C. The SOI chip is shown to have more significant performance improvement at low temperatures compared to bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The low temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At -30/spl deg/C the register file is capable of functioning close to 1.02 GHz for read and write operations in a single cycle.