哈希表在模拟电路合成中的应用

Almitra Pradhan, R. Vemuri
{"title":"哈希表在模拟电路合成中的应用","authors":"Almitra Pradhan, R. Vemuri","doi":"10.1109/VLSI.2008.35","DOIUrl":null,"url":null,"abstract":"Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"On the Use of Hash Tables for Efficient Analog Circuit Synthesis\",\"authors\":\"Almitra Pradhan, R. Vemuri\",\"doi\":\"10.1109/VLSI.2008.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.\",\"PeriodicalId\":143886,\"journal\":{\"name\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"21st International Conference on VLSI Design (VLSID 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI.2008.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

实现准确和快速的电路尺寸是自动化模拟合成的一个挑战。基于系统矩阵模型的估计器能准确地预测电路性能。在本文中,我们将哈希与矩阵模型结合使用,以获得更快的综合收敛速度。哈希表避免了一些矩阵元素的重新计算,从而缩短了合成时间。通过将矩阵元素划分为类并构建类哈希表,可以有效地执行哈希。哈希表在几次合成运行中更新,这进一步加快了收敛速度。实验结果表明,与使用宏模型但不使用哈希的综合方法相比,该方法可以提供4 -6倍的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
On the Use of Hash Tables for Efficient Analog Circuit Synthesis
Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Memory Design and Advanced Semiconductor Technology A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits IEEE Market-Oriented Standards Process and the EDA Industry Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1