{"title":"SBNR浮点约定","authors":"O. Morales","doi":"10.1109/REG5.1988.15889","DOIUrl":null,"url":null,"abstract":"Three conflicting needs are identified in real-time scientific and military applications: high precision, to minimize rounding errors; wide dynamic range, to avoid overflow; and speed, to accommodate wideband signals. These three requirements are mutually exclusive in the sense that higher accuracy and wider range usually entail a decrease in throughput. To resolve the conflict, a floating-point signed-binary-number representation (SBNR) is described that exploits all of the characteristics of a redundant number system, while providing the wide dynamic range desired. When coupled with multiple-value logic (MVL), the proposed implementation is considered to offer potential for reducing on-chip interconnect area, and thus for minimizing chip pin-out, without exacerbating the already critical reliability issues.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An SBNR floating-point convention\",\"authors\":\"O. Morales\",\"doi\":\"10.1109/REG5.1988.15889\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Three conflicting needs are identified in real-time scientific and military applications: high precision, to minimize rounding errors; wide dynamic range, to avoid overflow; and speed, to accommodate wideband signals. These three requirements are mutually exclusive in the sense that higher accuracy and wider range usually entail a decrease in throughput. To resolve the conflict, a floating-point signed-binary-number representation (SBNR) is described that exploits all of the characteristics of a redundant number system, while providing the wide dynamic range desired. When coupled with multiple-value logic (MVL), the proposed implementation is considered to offer potential for reducing on-chip interconnect area, and thus for minimizing chip pin-out, without exacerbating the already critical reliability issues.<<ETX>>\",\"PeriodicalId\":126733,\"journal\":{\"name\":\"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/REG5.1988.15889\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REG5.1988.15889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Three conflicting needs are identified in real-time scientific and military applications: high precision, to minimize rounding errors; wide dynamic range, to avoid overflow; and speed, to accommodate wideband signals. These three requirements are mutually exclusive in the sense that higher accuracy and wider range usually entail a decrease in throughput. To resolve the conflict, a floating-point signed-binary-number representation (SBNR) is described that exploits all of the characteristics of a redundant number system, while providing the wide dynamic range desired. When coupled with multiple-value logic (MVL), the proposed implementation is considered to offer potential for reducing on-chip interconnect area, and thus for minimizing chip pin-out, without exacerbating the already critical reliability issues.<>