Xin Wang, S. Fan, B. Qin, Jian Liu, Lin Lin, He Tang, H Zhao, Q. Fang, Albert Z. H. Wang, J. He, B. Zhao, R. Wong, Shi-Jie Wen
{"title":"RFCMOS中具有8kV+ ESD保护的全频带UWB LNA","authors":"Xin Wang, S. Fan, B. Qin, Jian Liu, Lin Lin, He Tang, H Zhao, Q. Fang, Albert Z. H. Wang, J. He, B. Zhao, R. Wong, Shi-Jie Wen","doi":"10.1109/RWS.2011.5725431","DOIUrl":null,"url":null,"abstract":"This paper reports a single-chip full-band 3.1–10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18µm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak gain of 10.9dB, a good gain flatness of 3.64%/GHz across 3.1–10.6GHz, low input reflection of <−10dB, noise figure of 4.98dB, group delay of 103±35pS and good linearity with P1-dB=2.88dBm@7GHz.","PeriodicalId":250672,"journal":{"name":"2011 IEEE Radio and Wireless Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Full band UWB LNA with 8kV+ ESD protection in RFCMOS\",\"authors\":\"Xin Wang, S. Fan, B. Qin, Jian Liu, Lin Lin, He Tang, H Zhao, Q. Fang, Albert Z. H. Wang, J. He, B. Zhao, R. Wong, Shi-Jie Wen\",\"doi\":\"10.1109/RWS.2011.5725431\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports a single-chip full-band 3.1–10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18µm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak gain of 10.9dB, a good gain flatness of 3.64%/GHz across 3.1–10.6GHz, low input reflection of <−10dB, noise figure of 4.98dB, group delay of 103±35pS and good linearity with P1-dB=2.88dBm@7GHz.\",\"PeriodicalId\":250672,\"journal\":{\"name\":\"2011 IEEE Radio and Wireless Symposium\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Radio and Wireless Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2011.5725431\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2011.5725431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Full band UWB LNA with 8kV+ ESD protection in RFCMOS
This paper reports a single-chip full-band 3.1–10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18µm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak gain of 10.9dB, a good gain flatness of 3.64%/GHz across 3.1–10.6GHz, low input reflection of <−10dB, noise figure of 4.98dB, group delay of 103±35pS and good linearity with P1-dB=2.88dBm@7GHz.