采用90nm CMOS技术的高性能20-T混合式全加法器

2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE) Pub Date : 2019-11-01 DOI:10.1109/WITCONECE48374.2019.9092897

Jyoti Kandpal, A. Tomar, Kailash Pandey, Mayur Agarwal

{"title":"采用90nm CMOS技术的高性能20-T混合式全加法器","authors":"Jyoti Kandpal, A. Tomar, Kailash Pandey, Mayur Agarwal","doi":"10.1109/WITCONECE48374.2019.9092897","DOIUrl":null,"url":null,"abstract":"In this paper, a high-performance full adder design is proposed using the hybrid logic style. There are three modules in the hybrid logic structure. The module I generates the XOR/XNOR output simultaneously whereas module II and module III are realized using the XOR/XNOR and CIN signal. The proposed design is simulated in the cadence software using the 90 nm CMOS technology at 1.2V. The proposed design gives the improvement 53% and 57 % in terms of delay and PDP, respectively when compared with its best counterpart. The proposed circuit also performs well with different supply voltage.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology\",\"authors\":\"Jyoti Kandpal, A. Tomar, Kailash Pandey, Mayur Agarwal\",\"doi\":\"10.1109/WITCONECE48374.2019.9092897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a high-performance full adder design is proposed using the hybrid logic style. There are three modules in the hybrid logic structure. The module I generates the XOR/XNOR output simultaneously whereas module II and module III are realized using the XOR/XNOR and CIN signal. The proposed design is simulated in the cadence software using the 90 nm CMOS technology at 1.2V. The proposed design gives the improvement 53% and 57 % in terms of delay and PDP, respectively when compared with its best counterpart. The proposed circuit also performs well with different supply voltage.\",\"PeriodicalId\":350816,\"journal\":{\"name\":\"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WITCONECE48374.2019.9092897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WITCONECE48374.2019.9092897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

本文提出了一种采用混合逻辑方式的高性能全加法器设计方案。在混合逻辑结构中有三个模块。模块I同时产生XOR/XNOR输出，而模块II和模块III使用XOR/XNOR和CIN信号实现。该设计在cadence软件中使用1.2V的90nm CMOS技术进行了仿真。与最佳设计相比，该设计在延迟和PDP方面分别提高了53%和57%。该电路在不同的电源电压下也具有良好的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology

In this paper, a high-performance full adder design is proposed using the hybrid logic style. There are three modules in the hybrid logic structure. The module I generates the XOR/XNOR output simultaneously whereas module II and module III are realized using the XOR/XNOR and CIN signal. The proposed design is simulated in the cadence software using the 90 nm CMOS technology at 1.2V. The proposed design gives the improvement 53% and 57 % in terms of delay and PDP, respectively when compared with its best counterpart. The proposed circuit also performs well with different supply voltage.

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2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)

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