{"title":"基于virtex-5 FPGA的SEU检测与校正监控系统的开发","authors":"Vijay Savani, Nagendra P. Gajjar","doi":"10.1109/NUICONE.2011.6153268","DOIUrl":null,"url":null,"abstract":"In the present era of space application, use of FPGA has been increase dramatically and because of that the developed SEU Monitor System can be used to inject the error manually into the FPGA and after that detection and correction can be confirmed. Also, injected error can be used to verify the effectiveness of the mitigation technique added into the design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.","PeriodicalId":206392,"journal":{"name":"2011 Nirma University International Conference on Engineering","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Development of SEU Monitor System for SEU detection and correction in virtex-5 FPGA\",\"authors\":\"Vijay Savani, Nagendra P. Gajjar\",\"doi\":\"10.1109/NUICONE.2011.6153268\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the present era of space application, use of FPGA has been increase dramatically and because of that the developed SEU Monitor System can be used to inject the error manually into the FPGA and after that detection and correction can be confirmed. Also, injected error can be used to verify the effectiveness of the mitigation technique added into the design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.\",\"PeriodicalId\":206392,\"journal\":{\"name\":\"2011 Nirma University International Conference on Engineering\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Nirma University International Conference on Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NUICONE.2011.6153268\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Nirma University International Conference on Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NUICONE.2011.6153268","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Development of SEU Monitor System for SEU detection and correction in virtex-5 FPGA
In the present era of space application, use of FPGA has been increase dramatically and because of that the developed SEU Monitor System can be used to inject the error manually into the FPGA and after that detection and correction can be confirmed. Also, injected error can be used to verify the effectiveness of the mitigation technique added into the design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.
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