一种基于空间划分和调度的并行确定性路由器

Chin Hau Hoo, Akash Kumar
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引用次数: 19

摘要

网络路由是FPGA设计流程中最耗时的步骤之一。现有的工作已经描述了通过并行化加速进程的方法。然而,其中只有一部分是确定性的,而确定性往往是以牺牲加速为代价的。在本文中,我们提出了一种基于空间划分的并行FPGA路由器ParaDRo,它在保持合理加速的同时实现了确定性的结果。现有的基于空间分区的路由器不能很好地扩展,因为可以充分利用所有处理器的网络数量随着处理器数量的增加而减少。此外,它们按顺序路由空间分区内的网络。如果一个空间分区内的网络没有重叠的边界框,ParaDRo通过调度网络并行路由来缓解这个问题。通过将多汇网分解为单汇网来进一步提取并行性,以最小化边界框重叠的数量,并增加可以并行路由的网的数量。这些改进使ParaDRo能够在8个线程的情况下实现5.4倍的平均加速,同时对结果质量的影响最小。
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ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling
Routing of nets is one of the most time-consuming steps in the FPGA design flow. Existing works have described ways of accelerating the process through parallelization. However, only some of them are deterministic, and determinism is often achieved at the cost of speedup. In this paper, we propose ParaDRo, a parallel FPGA router based on spatial partitioning that achieves deterministic results while maintaining reasonable speedup. Existing spatial partitioning based routers do not scale well because the number of nets that can fully utilize all processors reduces as the number of processors increases. In addition, they route nets that are within a spatial partition sequentially. ParaDRo mitigates this problem by scheduling nets within a spatial partition to be routed in parallel if they do not have overlapping bounding boxes. Further parallelism is extracted by decomposing multi-sink nets into single-sink nets to minimize the amount of bounding box overlaps and increase the number of nets that can be routed in parallel. These improvements enable ParaDRo to achieve an average speedup of 5.4X with 8 threads with minimal impact on the quality of results.
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Architecture and Circuit Design of an All-Spintronic FPGA Session details: Session 6: High Level Synthesis 2 A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only) Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only) Session details: Special Session: Deep Learning
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