{"title":"VLSI实现相机数字信号处理器的文件投影系统","authors":"Shih-Chang Hsia, Po-Shien Tsai","doi":"10.1109/ICSPS.2010.5555444","DOIUrl":null,"url":null,"abstract":"The camera digital signal processing (DSP) core is a key component for a video catching system. In this study, first high-performance and low-complexity algorithms are developed for the camera DSP system. The main functions involve the color interpolation, white balance, color space transformation, auto gain control, edge enhancement and color enhancement. Simulations demonstrate that the proposed method can achieve good quality as for a color-filter-array format camera. Based on the algorithms, the DSP processor is developed with pipelined structure. The prototyping chip is verified with one FPGA device, and then its ASIC is also realized with 0.35um CMOS process. A real-time camera system with 1270×792 resolutions is successfully demonstrated by the combination with the extra components within one PCB broad.","PeriodicalId":234084,"journal":{"name":"2010 2nd International Conference on Signal Processing Systems","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"VLSI implementation of camera digital signal processor for document projection system\",\"authors\":\"Shih-Chang Hsia, Po-Shien Tsai\",\"doi\":\"10.1109/ICSPS.2010.5555444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The camera digital signal processing (DSP) core is a key component for a video catching system. In this study, first high-performance and low-complexity algorithms are developed for the camera DSP system. The main functions involve the color interpolation, white balance, color space transformation, auto gain control, edge enhancement and color enhancement. Simulations demonstrate that the proposed method can achieve good quality as for a color-filter-array format camera. Based on the algorithms, the DSP processor is developed with pipelined structure. The prototyping chip is verified with one FPGA device, and then its ASIC is also realized with 0.35um CMOS process. A real-time camera system with 1270×792 resolutions is successfully demonstrated by the combination with the extra components within one PCB broad.\",\"PeriodicalId\":234084,\"journal\":{\"name\":\"2010 2nd International Conference on Signal Processing Systems\",\"volume\":\"8 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 2nd International Conference on Signal Processing Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSPS.2010.5555444\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 2nd International Conference on Signal Processing Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPS.2010.5555444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VLSI implementation of camera digital signal processor for document projection system
The camera digital signal processing (DSP) core is a key component for a video catching system. In this study, first high-performance and low-complexity algorithms are developed for the camera DSP system. The main functions involve the color interpolation, white balance, color space transformation, auto gain control, edge enhancement and color enhancement. Simulations demonstrate that the proposed method can achieve good quality as for a color-filter-array format camera. Based on the algorithms, the DSP processor is developed with pipelined structure. The prototyping chip is verified with one FPGA device, and then its ASIC is also realized with 0.35um CMOS process. A real-time camera system with 1270×792 resolutions is successfully demonstrated by the combination with the extra components within one PCB broad.