{"title":"用于宽带CDMA WLL系统的反向链路接收专用集成电路","authors":"Y. Jeong, J. Chung","doi":"10.1109/ICPWC.1997.655545","DOIUrl":null,"url":null,"abstract":"The wireless local loop (WLL) is an access system that uses a wireless link to connect subscribers to their local exchange in place of conventional copper cable. We propose a common air interface for a wideband CDMA WLL system. This paper describes the design and implementation of a digital receiver ASIC for the proposed wideband CDMA WLL system. The proposed reverse link transmitter structure is described followed by the design specification of the reverse link receiver. The operation of the implemented reverse link receiver ASIC is verified by the system timing simulation. The total gate number of the receiver ASIC including the code acquisition module, code tracking and data demodulation module, and the Viterbi decoder module is about 150,000. For the purpose of the ASIC implementation, 0.6 /spl mu/m CMOS technology is used. The implemented reverse link receiver ASIC can operate at clock frequencies of up to 65.536 MHz.","PeriodicalId":166667,"journal":{"name":"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Reverse link receiver ASIC for wideband CDMA WLL system\",\"authors\":\"Y. Jeong, J. Chung\",\"doi\":\"10.1109/ICPWC.1997.655545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The wireless local loop (WLL) is an access system that uses a wireless link to connect subscribers to their local exchange in place of conventional copper cable. We propose a common air interface for a wideband CDMA WLL system. This paper describes the design and implementation of a digital receiver ASIC for the proposed wideband CDMA WLL system. The proposed reverse link transmitter structure is described followed by the design specification of the reverse link receiver. The operation of the implemented reverse link receiver ASIC is verified by the system timing simulation. The total gate number of the receiver ASIC including the code acquisition module, code tracking and data demodulation module, and the Viterbi decoder module is about 150,000. For the purpose of the ASIC implementation, 0.6 /spl mu/m CMOS technology is used. The implemented reverse link receiver ASIC can operate at clock frequencies of up to 65.536 MHz.\",\"PeriodicalId\":166667,\"journal\":{\"name\":\"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICPWC.1997.655545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE International Conference on Personal Wireless Communications (Cat. No.97TH8338)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPWC.1997.655545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reverse link receiver ASIC for wideband CDMA WLL system
The wireless local loop (WLL) is an access system that uses a wireless link to connect subscribers to their local exchange in place of conventional copper cable. We propose a common air interface for a wideband CDMA WLL system. This paper describes the design and implementation of a digital receiver ASIC for the proposed wideband CDMA WLL system. The proposed reverse link transmitter structure is described followed by the design specification of the reverse link receiver. The operation of the implemented reverse link receiver ASIC is verified by the system timing simulation. The total gate number of the receiver ASIC including the code acquisition module, code tracking and data demodulation module, and the Viterbi decoder module is about 150,000. For the purpose of the ASIC implementation, 0.6 /spl mu/m CMOS technology is used. The implemented reverse link receiver ASIC can operate at clock frequencies of up to 65.536 MHz.