Estimation of high speed encoder with MTCMOS technique in 45 nanometer era

High performance 4:2 Encoder design using standard CMOS (Complementary Metal Oxide Semiconductor) logic gates is proposed. The proposed encoder design implementation accommodates both high and low current/power characteristics with scalable design structure through MTCMOS (Multi threshold CMOS) technique. This technique is applied to minimize the entire power and shows significant improvement in terms of speed. During the simulation we simulate the encoder by regular CMOS scheme and then proposed MTCMOS technique consists of sleep transistors connect with the logic circuit. The leakage current reduces to 54.56% and leakage power is 57.71%.