VLSI Implementation of Multiplier and Adder Circuits with Vedic Algorithm Computation

This work aims to build a Vedic Multiplier using the Indian Vedic Mathematics technique as the best alternative for multiplying algorithm. The performance of a high-speed CPU is heavily dependent on a component known as a multiplier. In this project, we will use the Vedic mathematics algorithm with detector and compressor circuits to overcome these major challenges of delay and complexity. We will focus on minimizing the processing delay of the digital circuit thereby increasing the speed. Also, reducing the switching activities, that will reduce the power consumption. The algorithm that we will use is ‘Urdhva-Tiryagbhyam Sutra’. Simulation will be done using Xilinx ISE platform with Verilog language. Finally, the goal of this study is to design an effective Vedic Multiplier employing the Urdhva-Tiryabhyam algorithm, followed by a comparison of the proposed and conventional multipliers based on area, propagation delay, and power, with improved performance factors.