Efficient Built in Self Repair for Multiple RAMs

With increase in memory dimensions and complexity, the VLSI manufacturing units are working on improving the features of memory dice for bigger capacities. Fault tolerant techniques are employed to take care of increased faults as the probability faults are increasing with increase in memory size. This is achieved by incorporating built-in redundancy analysis (BIRA) into the chip. For multiple memories of SoC, simple spare structure with local spares and columns is inadequate as optimum repair rate and area overhead are not obtained. So the proposed work global spares are incorporated in addition to local spares to enhance the yield and reduce hardware overhead. The proposed algorithm searches these various spares efficiently resulting in less hardware overhead with quick analysis.