16-Bit Low Power Feedforward Architecture Sigma-Delta ADC with Integrator Time Multiplexing for Microprocessors

This study presents a design of low power 3rd order 16-bit Sigma Delta Analog to Digital Converter in Feedforward Architecture with Integrator Time Multiplexing Technique implemented in TSMC 65nm CMOS technology. The designed is composed of a 3rd-order modulator in feedforward architecture to improve loop stability and with integrator time multiplexing technique for reduction of power consumption. The Analog to Digital Converter (ADC) is designed to consume a total power of 0.342mW and with a modulator sampling rate of 25600Hz. This ADC uses a 2V supply for analog circuit blocks and a 1V supply for digital circuit block. The ADC has a dimension of 333.35um x 241.64um.