Peak power identification on power bumps during test application

Peak power during test can seriously impact circuit performance as well as the power safety for both CUT and tester. In this paper, we propose a method of layout-aware weighted switching activity identification flow that evaluates peak current/power on power bumps to detect high power patterns. The dynamic power model uses load capacitance as a metric to represent its value. Parasitic capacitance is also extracted from layout and taken into account in calculating power. Resistance network is considered regarding power bus to determine the power delivery path and power level on each specific power bump. The peak power identification flow can be integrated in gate level pattern simulation that the IR-drop results have good correlation with commercial power sign-off analysis tool.