异构系统中高效的数据并行基元

Zhuohang Lai, Qiong Luo, Xiaolong Xie
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引用次数: 2

摘要

数据并行原语,如gather、scatter、scan和split,广泛用于数据密集型应用程序。然而,在由异构处理器组成的系统上优化它们是具有挑战性的。在本文中,我们研究和比较了一组数据并行原语在GPU、CPU和Xeon Phi协处理器上的现有实现和优化策略。我们的目标是确定在不同架构上实现数据并行原语操作的关键性能因素,并开发在各种平台上有效实现这些原语的通用策略。我们引入了一种可移植且高效的顺序存储器访问模式,消除了为单个设备调整存储器访问模式的成本。通过适当的调优,我们优化的原语实现可以达到与本机版本相当的性能。此外,我们的分析结果表明,CPU和Phi协处理器共享大多数优化策略,而GPU由于这些设备之间的硬件差异而差异很大,例如向量化,数据和TLB缓存以及数据预取的效率。我们总结了这些因素,并为异构系统提供了通用的原始优化策略。
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Efficient Data-Parallel Primitives on Heterogeneous Systems
Data-parallel primitives, such as gather, scatter, scan, and split, are widely used in data-intensive applications. However, it is challenging to optimize them on a system consisting of heterogeneous processors. In this paper, we study and compare the existing implementations and optimization strategies for a set of data-parallel primitives on three processors: GPU, CPU and Xeon Phi co-processor. Our goal is to identify the key performance factors in the implementations of data-parallel primitive operations on different architectures and develop general strategies for implementing these primitives efficiently on various platforms. We introduce a portable and efficient sequential memory access pattern, which eliminates the cost of adjusting the memory access pattern for individual device. With proper tuning, our optimized primitive implementations can achieve comparable performance to the native versions. Moreover, our profiling results show that the CPU and the Phi co-processor share most optimization strategies whereas the GPU differs from them significantly, due to the hardware differences among these devices, such as efficiency of vectorization, data and TLB caching, and data prefetching. We summarize these factors and deliver common primitive optimization strategies for heterogeneous systems.
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