{"title":"一个高速Prolog解释器的实现","authors":"A. Krall","doi":"10.1145/29650.29663","DOIUrl":null,"url":null,"abstract":"This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.","PeriodicalId":414056,"journal":{"name":"SIGPLAN Conferences and Workshops","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Implementation of a high-speed Prolog interpreter\",\"authors\":\"A. Krall\",\"doi\":\"10.1145/29650.29663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.\",\"PeriodicalId\":414056,\"journal\":{\"name\":\"SIGPLAN Conferences and Workshops\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1987-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"SIGPLAN Conferences and Workshops\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/29650.29663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"SIGPLAN Conferences and Workshops","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/29650.29663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.
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