Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform

The power wall is a barrier to improving the processor design process due to the power consumption of components. The usage of heterogeneous multicore platforms is appealing for applications, e.g. hard real-time systems, owing to the potential reduced energy consumption offered by such platforms. However, hard real-time systems are present in life critical environments and reducing the energy consumption on such systems is an onerous and complex process. This paper assesses the problem of providing response time schedulability conditions for hard real-time systems on cluster-based platforms. We extend the existing theory with a novel schedulability test that accounts for the natural latency inherited from the usage of DVFS. We also compare our approach with state of the art methods by means of empirical experiments. Our proposed response time schedulability test avoids up to 99% false positive and false negative errors observed in the well known schedulability analyses' literature.