{"title":"利用FPGA进行计算机体系结构/组织教育","authors":"Yamin Li, Wanming Chu","doi":"10.1145/1275152.1275157","DOIUrl":null,"url":null,"abstract":"In this paper, we introduce hardware exercises for Computer Architecture/Organization Education at the University of Aizu, Japan. Particularly, we discuss a pipelined RISC processor design and implementation on Xilinx FPGA chip.","PeriodicalId":344384,"journal":{"name":"WCAE-2 '96","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Using FPGA for computer architecture/organization education\",\"authors\":\"Yamin Li, Wanming Chu\",\"doi\":\"10.1145/1275152.1275157\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we introduce hardware exercises for Computer Architecture/Organization Education at the University of Aizu, Japan. Particularly, we discuss a pipelined RISC processor design and implementation on Xilinx FPGA chip.\",\"PeriodicalId\":344384,\"journal\":{\"name\":\"WCAE-2 '96\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"WCAE-2 '96\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1275152.1275157\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"WCAE-2 '96","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1275152.1275157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using FPGA for computer architecture/organization education
In this paper, we introduce hardware exercises for Computer Architecture/Organization Education at the University of Aizu, Japan. Particularly, we discuss a pipelined RISC processor design and implementation on Xilinx FPGA chip.
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