S. Matui, M. Yamamoto, I. Kawasaki, S. Narita, F. Arakawa, K. Uchiyama
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GMICRO/500 microprocessor: pipeline structure of superscalar architecture
The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones.<>
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