{"title":"用于相似距离计算的可扩展和可参数化处理器阵列架构","authors":"Awos Kanan, F. Gebali, Atef Ibrahim, K. F. Li","doi":"10.1109/IACS.2019.8809140","DOIUrl":null,"url":null,"abstract":"Processor array architecture is a popular approach to improve computation of similarity distance matrices; however, most of the proposed architectures are designed in an ad hoc manner, some have not even considered dimensionality and size of the datasets. We believe a systematic approach is necessary to explore the design space. In this work, we present a technique for designing scalable processor array architecture for the similarity distance matrix computation. Implementation results of the proposed architecture show improved compromise between area and speed. Moreover, it scales better for large and high-dimensional datasets since the architecture is fully parameterized and only has to deal with one data dimension in each time step.","PeriodicalId":225697,"journal":{"name":"2019 10th International Conference on Information and Communication Systems (ICICS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Scalable and Parameterizable Processor Array Architecture for Similarity Distance Computation\",\"authors\":\"Awos Kanan, F. Gebali, Atef Ibrahim, K. F. Li\",\"doi\":\"10.1109/IACS.2019.8809140\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Processor array architecture is a popular approach to improve computation of similarity distance matrices; however, most of the proposed architectures are designed in an ad hoc manner, some have not even considered dimensionality and size of the datasets. We believe a systematic approach is necessary to explore the design space. In this work, we present a technique for designing scalable processor array architecture for the similarity distance matrix computation. Implementation results of the proposed architecture show improved compromise between area and speed. Moreover, it scales better for large and high-dimensional datasets since the architecture is fully parameterized and only has to deal with one data dimension in each time step.\",\"PeriodicalId\":225697,\"journal\":{\"name\":\"2019 10th International Conference on Information and Communication Systems (ICICS)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 10th International Conference on Information and Communication Systems (ICICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IACS.2019.8809140\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 10th International Conference on Information and Communication Systems (ICICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IACS.2019.8809140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scalable and Parameterizable Processor Array Architecture for Similarity Distance Computation
Processor array architecture is a popular approach to improve computation of similarity distance matrices; however, most of the proposed architectures are designed in an ad hoc manner, some have not even considered dimensionality and size of the datasets. We believe a systematic approach is necessary to explore the design space. In this work, we present a technique for designing scalable processor array architecture for the similarity distance matrix computation. Implementation results of the proposed architecture show improved compromise between area and speed. Moreover, it scales better for large and high-dimensional datasets since the architecture is fully parameterized and only has to deal with one data dimension in each time step.