{"title":"三维标准芯片堆叠系统TSV数据流网络的FPGA仿真","authors":"Takeshi Ohkawa, M. Aoyagi","doi":"10.1109/COOLCHIPS57690.2023.10122025","DOIUrl":null,"url":null,"abstract":"Through-Silicon-Via (TSV) is expected to realize high-performance, low-power consumption, and lowcost 3D-LSI (Large Scale Integration) system. It is realized by integrating pre-manufactured chips with a 3D Standard Chip Stacking System (3D-SCSS) through a standard bus TSV connection. However, it is difficult to define a standard chip connection mechanism. This paper proposes an FPGA emulation of the TSV dataflow network for evaluating the performance of 3D-SCSS. To emulate 3D-SCSS, multiple-clock domains are assumed to overcome the problem of jitter in the global clock, which is a separated clock domain model. Simple dataflow experiments are done where processes are deployed to different chips and communicate among the chips in the 3D-SCSS. The evaluation shows that the emulation method is suitable to measure the latency performance of the proposed TSV dataflow network. (Keywords: 3D-LSI, TSV, FPGA, Emulation, Dataflow, 3D-SCSS)","PeriodicalId":387793,"journal":{"name":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System\",\"authors\":\"Takeshi Ohkawa, M. Aoyagi\",\"doi\":\"10.1109/COOLCHIPS57690.2023.10122025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Through-Silicon-Via (TSV) is expected to realize high-performance, low-power consumption, and lowcost 3D-LSI (Large Scale Integration) system. It is realized by integrating pre-manufactured chips with a 3D Standard Chip Stacking System (3D-SCSS) through a standard bus TSV connection. However, it is difficult to define a standard chip connection mechanism. This paper proposes an FPGA emulation of the TSV dataflow network for evaluating the performance of 3D-SCSS. To emulate 3D-SCSS, multiple-clock domains are assumed to overcome the problem of jitter in the global clock, which is a separated clock domain model. Simple dataflow experiments are done where processes are deployed to different chips and communicate among the chips in the 3D-SCSS. The evaluation shows that the emulation method is suitable to measure the latency performance of the proposed TSV dataflow network. (Keywords: 3D-LSI, TSV, FPGA, Emulation, Dataflow, 3D-SCSS)\",\"PeriodicalId\":387793,\"journal\":{\"name\":\"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COOLCHIPS57690.2023.10122025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COOLCHIPS57690.2023.10122025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System
Through-Silicon-Via (TSV) is expected to realize high-performance, low-power consumption, and lowcost 3D-LSI (Large Scale Integration) system. It is realized by integrating pre-manufactured chips with a 3D Standard Chip Stacking System (3D-SCSS) through a standard bus TSV connection. However, it is difficult to define a standard chip connection mechanism. This paper proposes an FPGA emulation of the TSV dataflow network for evaluating the performance of 3D-SCSS. To emulate 3D-SCSS, multiple-clock domains are assumed to overcome the problem of jitter in the global clock, which is a separated clock domain model. Simple dataflow experiments are done where processes are deployed to different chips and communicate among the chips in the 3D-SCSS. The evaluation shows that the emulation method is suitable to measure the latency performance of the proposed TSV dataflow network. (Keywords: 3D-LSI, TSV, FPGA, Emulation, Dataflow, 3D-SCSS)