Area and power efficient register allocation technique for the implementation of PCA

This paper presents a novel register allocation technique as well as the conventional technique for the implementation of Principal Component Analysis (PCA) incorporating variable reuse technique. PCA deals with a large dimensional data and is a computationally intensive technique. The purpose of this paper is to avoid register switching and hence reduction in dynamic power consumption as well as area during the implementation of PCA. Syntheses of verilog codes written for both the techniques were carried out in RC (cadence) tool. In case of generic synthesis, a substantial decrease of 56.867% in power and 56.66% in case of area was observed; whereas, in case of mapped synthesis, significant reduction of 86.145% in power and 74.79% in area was observed for the proposed technique in contrast to the conventional one.