Clock skew analysis based on NBTI degeneration of pMOSFET

In this paper, a set of formulas which are sensitive to the shift in threshold voltage (AVth) of PMOS transistor, load capacitance (CL), and input transition (ti) have been explored to calculate the propagation delay of CMOS inverter using curved surfaces fitting. Different from conventional of focusing on load capacitance and input transition, our proposed model pay more attention to the impact of AVth variation caused by NBTI degeneration on the propagation delay. Moreover, this paper has also proposed a framework to calculate the path delay and clock skew of clock tree network based on the proposed delay model. In order to validate our proposed models and methods, the SPICE-level simulation of the benchmark circuit (s38417) has been compared with our model calculation using a 45-nm CMOS process technology, the results show that our models and methods can calculate the extra path delay and clock skew caused by the shift in threshold voltage.