一个8毫安,3.8 dB NF, 40 dB增益CMOS前端GPS应用

F. Svelto, S. Deantoni, G. Montagna, R. Castello
{"title":"一个8毫安,3.8 dB NF, 40 dB增益CMOS前端GPS应用","authors":"F. Svelto, S. Deantoni, G. Montagna, R. Castello","doi":"10.1109/LPE.2000.155299","DOIUrl":null,"url":null,"abstract":"A fully differential 0.35 /spl mu/m CMOS LNA plus mixer, tailored to a double conversion architecture, for GPS applications has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by an MOS varactor. The mixer is a Gilbert cell like, in which an NMOS and a PMOS differential pair, shunted together, realize the input stage. This topology allows one to save power, for given mixer gain and linearity. The front-end measured performances are: 40 dB gain, 3.8 dB NF,-25.5 dBm IIP3, 1.3 GHz input frequency, 140 MHz output frequency, with 8 mA from a 2.8 V voltage supply.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications\",\"authors\":\"F. Svelto, S. Deantoni, G. Montagna, R. Castello\",\"doi\":\"10.1109/LPE.2000.155299\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully differential 0.35 /spl mu/m CMOS LNA plus mixer, tailored to a double conversion architecture, for GPS applications has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by an MOS varactor. The mixer is a Gilbert cell like, in which an NMOS and a PMOS differential pair, shunted together, realize the input stage. This topology allows one to save power, for given mixer gain and linearity. The front-end measured performances are: 40 dB gain, 3.8 dB NF,-25.5 dBm IIP3, 1.3 GHz input frequency, 140 MHz output frequency, with 8 mA from a 2.8 V voltage supply.\",\"PeriodicalId\":188020,\"journal\":{\"name\":\"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LPE.2000.155299\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LPE.2000.155299","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

一个全差分0.35 /spl mu/m CMOS LNA加混频器,专为双转换架构,GPS应用已经实现。LNA利用电感退化输入级和谐振LC负载,具有12%的频率调谐,由MOS变容管完成。混频器是吉尔伯特单元,其中NMOS和PMOS差分对并联在一起,实现输入级。在给定混频器增益和线性度的情况下,这种拓扑结构可以节省功率。前端测量性能为:40 dB增益,3.8 dB NF,-25.5 dBm IIP3, 1.3 GHz输入频率,140 MHz输出频率,2.8 V电压,8ma。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications
A fully differential 0.35 /spl mu/m CMOS LNA plus mixer, tailored to a double conversion architecture, for GPS applications has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by an MOS varactor. The mixer is a Gilbert cell like, in which an NMOS and a PMOS differential pair, shunted together, realize the input stage. This topology allows one to save power, for given mixer gain and linearity. The front-end measured performances are: 40 dB gain, 3.8 dB NF,-25.5 dBm IIP3, 1.3 GHz input frequency, 140 MHz output frequency, with 8 mA from a 2.8 V voltage supply.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
"Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 /spl mu/m SOI and bulk technology Reliable low-power design in the presence of deep submicron noise Operating-system directed power reduction Model and analysis for combined package and on-chip power grid simulation Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1