{"title":"超分辨率算法在FPGA上的实现","authors":"Sharayu Hurdale, P. Khandekar","doi":"10.1109/ICCIC.2015.7435757","DOIUrl":null,"url":null,"abstract":"Super resolution technique gives an effective way to increase image resolution. Lower resolution is converted into higher resolution. By proposed super resolution algorithm, image is resolved sixteen times. This paper presents a FPGA (Field Programmable Gate Array) implementation of super resolution algorithm. FPGA is used because of its various advantages. In super resolution image size is increased by adopting information from input image itself. Using this algorithm image can be resolved up-to 2x, 4x, 8x and 16x.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of super-resolution algorithm on FPGA\",\"authors\":\"Sharayu Hurdale, P. Khandekar\",\"doi\":\"10.1109/ICCIC.2015.7435757\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Super resolution technique gives an effective way to increase image resolution. Lower resolution is converted into higher resolution. By proposed super resolution algorithm, image is resolved sixteen times. This paper presents a FPGA (Field Programmable Gate Array) implementation of super resolution algorithm. FPGA is used because of its various advantages. In super resolution image size is increased by adopting information from input image itself. Using this algorithm image can be resolved up-to 2x, 4x, 8x and 16x.\",\"PeriodicalId\":276894,\"journal\":{\"name\":\"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCIC.2015.7435757\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIC.2015.7435757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of super-resolution algorithm on FPGA
Super resolution technique gives an effective way to increase image resolution. Lower resolution is converted into higher resolution. By proposed super resolution algorithm, image is resolved sixteen times. This paper presents a FPGA (Field Programmable Gate Array) implementation of super resolution algorithm. FPGA is used because of its various advantages. In super resolution image size is increased by adopting information from input image itself. Using this algorithm image can be resolved up-to 2x, 4x, 8x and 16x.
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