65纳米CMOS的6.5kV esd保护低噪声放大器

M. Tsai, F. Hsueh, C. Jou, Ming-Hsiang Song, J. Tseng, S. Hsu, Sean Chen
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引用次数: 3

摘要

提出了一种用于射频低噪声放大器(LNA)的新型ESD拓扑。采用改进的硅控整流器(MSCR)与P+/ n阱二极管钳位相结合,采用65纳米CMOS技术演示了5.8 ghz LNA与6.5 kv ESD保护电路。与参考设计相比,新拓扑将人体模型(HBM)的ESD电平从3.5 kV提高到6.5 kV,而噪声系数(NF)仅提高0.13 dB。在电源电压为1.2 V,漏极电流为6.5 mA的情况下,所提出的esd保护LNA的NF为2.57 dB,相关功率增益为16.7 dB。输入三阶截距点(IIP3)为−11 dBm,输入和输出回波损耗分别低于−15.9 dB和−20 dB。
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A 6.5kV ESD-protected low noise amplifier in 65-nm CMOS
A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P+/N-well diode clamp, a 5.8-GHz LNA with 6.5-kV ESD protection circuit is demonstrated by a 65-nm CMOS technology. Compared with the reference design, the new topology enhances the ESD level from 3.5 kV to 6.5 kV for human body model (HBM) while the noise figure (NF) is only 0.13 dB higher. Under a supply voltage of 1.2 V and drain current of 6.5 mA, the proposed ESD-protected LNA has a NF of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is −11 dBm and the input and output return losses are below −15.9 dB and −20 dB, respectively.
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