R. Meka, M. Sloderbeck, M. Faruque, J. Langston, M. Steurer, L. DeBrunner
{"title":"RTDS电力系统协同仿真中高频电力电子变换器的FPGA模型","authors":"R. Meka, M. Sloderbeck, M. Faruque, J. Langston, M. Steurer, L. DeBrunner","doi":"10.1109/ESTS.2013.6523714","DOIUrl":null,"url":null,"abstract":"This paper presents the work being done in developing Field Programmable Gate Array (FPGA) based high-frequency power electronic models in co-simulation with Real Time Digital Simulator (RTDS) small time step models. With the inclusion of FPGAs in the Electromagnetic Transient simulations, higher frequencies for power electronic models, which were not previously possible using only RTDS, can be achieved. A two port buck converter is modeled on an FPGA using Dommel's algorithm and interfaced with the small time-step environment in RTDS using a travelling wave model. The RTDS small time-step size is 2 μs, whereas the time-step for the FPGA is 300 ns. This paper presents the results and challenges faced in developing this system.","PeriodicalId":119318,"journal":{"name":"2013 IEEE Electric Ship Technologies Symposium (ESTS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"FPGA model of a high-frequency power electronic converter in an RTDS power system co-simulation\",\"authors\":\"R. Meka, M. Sloderbeck, M. Faruque, J. Langston, M. Steurer, L. DeBrunner\",\"doi\":\"10.1109/ESTS.2013.6523714\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the work being done in developing Field Programmable Gate Array (FPGA) based high-frequency power electronic models in co-simulation with Real Time Digital Simulator (RTDS) small time step models. With the inclusion of FPGAs in the Electromagnetic Transient simulations, higher frequencies for power electronic models, which were not previously possible using only RTDS, can be achieved. A two port buck converter is modeled on an FPGA using Dommel's algorithm and interfaced with the small time-step environment in RTDS using a travelling wave model. The RTDS small time-step size is 2 μs, whereas the time-step for the FPGA is 300 ns. This paper presents the results and challenges faced in developing this system.\",\"PeriodicalId\":119318,\"journal\":{\"name\":\"2013 IEEE Electric Ship Technologies Symposium (ESTS)\",\"volume\":\"114 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Electric Ship Technologies Symposium (ESTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESTS.2013.6523714\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Electric Ship Technologies Symposium (ESTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTS.2013.6523714","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA model of a high-frequency power electronic converter in an RTDS power system co-simulation
This paper presents the work being done in developing Field Programmable Gate Array (FPGA) based high-frequency power electronic models in co-simulation with Real Time Digital Simulator (RTDS) small time step models. With the inclusion of FPGAs in the Electromagnetic Transient simulations, higher frequencies for power electronic models, which were not previously possible using only RTDS, can be achieved. A two port buck converter is modeled on an FPGA using Dommel's algorithm and interfaced with the small time-step environment in RTDS using a travelling wave model. The RTDS small time-step size is 2 μs, whereas the time-step for the FPGA is 300 ns. This paper presents the results and challenges faced in developing this system.