具有30-ps 120 k逻辑门和片上测试电路的0.9 ns 1.15 mb ECL-CMOS SRAM

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI:10.1109/BIPOL.1995.493863

K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta

{"title":"具有30-ps 120 k逻辑门和片上测试电路的0.9 ns 1.15 mb ECL-CMOS SRAM","authors":"K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta","doi":"10.1109/BIPOL.1995.493863","DOIUrl":null,"url":null,"abstract":"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry\",\"authors\":\"K. Higeta, M. Usami, M. Ohayashi, Y. Fujimura, Masahiko Nishiyama, S. Isomura, K. Yamaguchi, Y. Idei, H. Nambu, K. Ohhata, Nadateru Hanta\",\"doi\":\"10.1109/BIPOL.1995.493863\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.\",\"PeriodicalId\":230944,\"journal\":{\"name\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1995.493863\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1995.493863","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

开发了一种具有30-ps 120 k逻辑门的0.9 ns 1.15 mb ECL-CMOS SRAM。为了提供良好的可测试性、可靠性和稳定性，提出了片上测试电路、存储单元测试技术、高稳定电流源和软错误免疫存储单元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting

自引率

0.00%

发文量

期刊最新文献

A BiCMOS fully-differential 10-bit 40 MHz pipelined ADC Efficient parameter extraction for the MEXTRAM model Improved collector transit time with ballistic pipi-structure in the npn-AlGaAs/GaAs HBT Silicon bipolar 12 GHz downconverter for satellite receivers Predictive modelling of lateral scaling in bipolar transistors