{"title":"用于OFDM接收机的模拟/混合信号快速傅里叶变换处理器IC原型","authors":"M. Lehne, S. Raman","doi":"10.1109/RWS.2008.4463614","DOIUrl":null,"url":null,"abstract":"A prototype FFT processor IC that reduces linearity requirements of analog-to-digital converters in broadband orthogonal-frequency-division-multiplexing (OFDM) receivers is presented. The processor is based on a time-interleaving bank of sample-and-holds and a discrete- time analog multiplication based FFT. The circuit design of the prototype IC is presented and measurement results from the 0.13 mum test chip are shown. The FFT length-8 prototype successfully demodulates a complex OFDM signal at 1 GSps while drawing 25 milliwatts of power from a 1.2 Volt supply and achieving an error vector magnitude of 2.8%.","PeriodicalId":431471,"journal":{"name":"2008 IEEE Radio and Wireless Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A prototype analog/mixed-signal fast fourier transform processor IC for OFDM receivers\",\"authors\":\"M. Lehne, S. Raman\",\"doi\":\"10.1109/RWS.2008.4463614\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A prototype FFT processor IC that reduces linearity requirements of analog-to-digital converters in broadband orthogonal-frequency-division-multiplexing (OFDM) receivers is presented. The processor is based on a time-interleaving bank of sample-and-holds and a discrete- time analog multiplication based FFT. The circuit design of the prototype IC is presented and measurement results from the 0.13 mum test chip are shown. The FFT length-8 prototype successfully demodulates a complex OFDM signal at 1 GSps while drawing 25 milliwatts of power from a 1.2 Volt supply and achieving an error vector magnitude of 2.8%.\",\"PeriodicalId\":431471,\"journal\":{\"name\":\"2008 IEEE Radio and Wireless Symposium\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Radio and Wireless Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2008.4463614\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2008.4463614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A prototype analog/mixed-signal fast fourier transform processor IC for OFDM receivers
A prototype FFT processor IC that reduces linearity requirements of analog-to-digital converters in broadband orthogonal-frequency-division-multiplexing (OFDM) receivers is presented. The processor is based on a time-interleaving bank of sample-and-holds and a discrete- time analog multiplication based FFT. The circuit design of the prototype IC is presented and measurement results from the 0.13 mum test chip are shown. The FFT length-8 prototype successfully demodulates a complex OFDM signal at 1 GSps while drawing 25 milliwatts of power from a 1.2 Volt supply and achieving an error vector magnitude of 2.8%.
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