一种用于2.5 Gb/s SDH接收机的低功耗时钟和数据恢复电路

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Pub Date : 2000-08-01 DOI:10.1145/344166.344202

A. Pallotta, F. Centurelli, A. Trifiletti

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引用次数: 4

摘要

采用Maxim GST-2 27ghz -f/sub - T/硅双极技术，设计并制作了一款适用于2.5 Gb/s SDH STM-16系统的低功耗单片时钟和数据恢复IC。该电路具有以下功能:信号放大与限制、时钟恢复与判定;单路3.3 V供电，功耗低于350mw。这种集成电路和先前提出的跨阻放大器可以组成一个总功耗低于0.5 W的接收器芯片组。在2/sup 23/-1 PRBS数据流下的初步测量显示，输入灵敏度低于20 mVpp，有效值抖动为10 ps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low-power Clock and Data Recovery circuit for 2.5 Gb/s SDH receivers

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f/sub T/ silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2/sup 23/-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.

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ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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