T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl
{"title":"带可控参考电路的LVDS I/O缓冲器","authors":"T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl","doi":"10.1109/ASIC.1997.617028","DOIUrl":null,"url":null,"abstract":"A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":"{\"title\":\"LVDS I/O buffers with a controlled reference circuit\",\"authors\":\"T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl\",\"doi\":\"10.1109/ASIC.1997.617028\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"31\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617028\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617028","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
LVDS I/O buffers with a controlled reference circuit
A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.
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