一种用于全集成数字ldo的零稳态偏移的新型热频时间量化器

Leiyi Wang, Chunfeng Bai, Heming Zhao
{"title":"一种用于全集成数字ldo的零稳态偏移的新型热频时间量化器","authors":"Leiyi Wang, Chunfeng Bai, Heming Zhao","doi":"10.1109/ICICM50929.2020.9292257","DOIUrl":null,"url":null,"abstract":"A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Novel Beat-Frequency Time Quantizer With Zero Steady-State Offset For Fully Integrated Digital LDOs\",\"authors\":\"Leiyi Wang, Chunfeng Bai, Heming Zhao\",\"doi\":\"10.1109/ICICM50929.2020.9292257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.\",\"PeriodicalId\":364285,\"journal\":{\"name\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM50929.2020.9292257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种具有零稳态偏移的新型热频时间量化器。基于该量化器的数字低差(DLDO)稳压器可以消除原有量化器带来的固有稳态输出误差,从而提高其输出精度(OA)。同时,该量化器保持了自适应采样时钟的特性。使其具有零稳态偏移、量化分辨率高、瞬态响应速度快、功耗低等优点。本文设计了基于40nm技术的量化器,并在1V电源电压下进行了仿真。仿真结果表明,其稳态偏移量为零。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A Novel Beat-Frequency Time Quantizer With Zero Steady-State Offset For Fully Integrated Digital LDOs
A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A Method of Impedance Imbalance Analysis for Passive Device A UVM Verification Platform for RISC-V SoC from Module to System Level The Property of ITO Produced by Optical Thin Film Coating for Solar Cell Research on Beam Widening of Rotman Lens A Multi-User Detector with Adaptive Iterative times in Scrambled Coded Multiple Access (SCMA) Systems
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1