{"title":"一种用于全集成数字ldo的零稳态偏移的新型热频时间量化器","authors":"Leiyi Wang, Chunfeng Bai, Heming Zhao","doi":"10.1109/ICICM50929.2020.9292257","DOIUrl":null,"url":null,"abstract":"A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Novel Beat-Frequency Time Quantizer With Zero Steady-State Offset For Fully Integrated Digital LDOs\",\"authors\":\"Leiyi Wang, Chunfeng Bai, Heming Zhao\",\"doi\":\"10.1109/ICICM50929.2020.9292257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.\",\"PeriodicalId\":364285,\"journal\":{\"name\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM50929.2020.9292257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Beat-Frequency Time Quantizer With Zero Steady-State Offset For Fully Integrated Digital LDOs
A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.