{"title":"关于FPGA板级路由问题","authors":"Xiaoyu Song, Yuke Wang","doi":"10.1109/CCECE.1998.682778","DOIUrl":null,"url":null,"abstract":"We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n/sup 2/) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration.","PeriodicalId":177613,"journal":{"name":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On the FPGA board level routing problem\",\"authors\":\"Xiaoyu Song, Yuke Wang\",\"doi\":\"10.1109/CCECE.1998.682778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n/sup 2/) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration.\",\"PeriodicalId\":177613,\"journal\":{\"name\":\"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.1998.682778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.1998.682778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n/sup 2/) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration.
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