{"title":"基于fpga的FIR滤波器采用数字串行算法","authors":"Hanho Lee, G. Sobelman","doi":"10.1109/ASIC.1997.617010","DOIUrl":null,"url":null,"abstract":"This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"FPGA-based FIR filters using digit-serial arithmetic\",\"authors\":\"Hanho Lee, G. Sobelman\",\"doi\":\"10.1109/ASIC.1997.617010\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617010\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617010","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA-based FIR filters using digit-serial arithmetic
This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.
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