一种基于40nm CMOS技术的320ghz四倍频器

Sun Ao di, Li Qin
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引用次数: 0

摘要

这封信提出了一个使用两级推推结构的四倍太赫兹(THz)倍增器[1]。采用Marchand Balun结构实现了一个80 GHz Balun和一个160 GHz Balun,实现了较好的幅值平衡和相位平衡性能以及较低的插入损耗。仿真结果表明,输出3dB带宽为70 GHz,范围为270 ~ 340 GHz。该四倍频器的变频损耗小于13 dB。同时,具有30db以上的良好基波抑制和8mw的低直流功耗。整个电路采用40纳米CMOS技术设计,面积为710 \mu\text{m} × 400\mu \text{m}}$,包括焊盘。
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A 320 GHz Frequency Quadrupler Based on 40 nm CMOS Technology
This letter presents a terahertz(THz) multiplier by four using two-stage push-push structure [1]. An 80 GHz Balun and a 160 GHz Balun are implemented by Marchand Balun structure and good performance of amplitude balance and phase balance are achieved as well as low insertion loss. The simulation results show that the output 3dB bandwidth is 70 GHz ranging from 270 GHz to 340 GHz. The quadruapler has a frequency conversion loss less than 13 dB. At the same time, good fundamental rejection greater than 30 dB and low DC power consumption 8 mW are achieved. The whole circuit is designed on 40 nm CMOS technology and occupies area of $\pmb{710 \mu\text{m} \times 400\mu \text{m}}$ including pads.
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