Use of Partial Reconfiguration for the Implementation and Embedding of the Artificial Neural Network (ANN) in FPGA

This paper is focused on partial reconfiguration of Field Programmable Gate Arrays (FPGAs) Virtex-6, produced by Xilinx, and its application implementing Artificial Neural Networks (ANNs) of Multilayer Perceptron (MLP) type. This FPGA can be partially reprogramed without suspending operation in other parts that do not need reconfiguration. It can be performed by specifying the Modular Project’s flow, where the modules that compose the project can be synthesized separately, and, after that, reunited in another module of highest hierarchical level. Alternatively, it is possible developing reconfigurable modules inserted in partial bitstreams and, later, downloading partial bitstreams successively in hardware. Therefore, it is possible configuring topologies of different MLP networks by using partial bitstreams in reconfigurable areas. It is expected that, in this kind of hardware, applications with MLP ANNs be easily embedded, and also allow easily configuration of many kinds of MLP networks in field.