用于高速应用的模拟解码器和接收器

J. Hagenauer, M. Moerz, A. Schaefer
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引用次数: 16

摘要

数据传输速度的不断提高,特别是在光通道、磁记录设备和无线链路中,使得有必要研究能够以低功耗进行高速处理的新型接收器结构。模拟、非线性和高度并行的工作电路可以执行均衡、差分检测、信道解码,在某些情况下还可以执行通常分配给数字处理器和电路的源解码任务。第一个简单解码器组件的原型模拟VLSI芯片已经可用,并且在高达10 Gbit/s的速度下表现良好。
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Analog decoders and receivers for high speed applications
The ever increasing speed of data transmission, especially in optical channels, in magnetic recording devices and in wireless links, makes it necessary to look at new receiver structures which are capable of high speed processing at low power consumption. Analog, nonlinear and highly parallel operating circuits can perform the tasks of equalization, differential detection, channel decoding and, in some cases, of source decoding which are normally assigned to digital processors and circuits. The first prototype analog VLSI chips of simple decoder components are available and perform well at speeds up to 10 Gbit/s.
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