模糊控制处理器体系结构模型

Proceedings of Tenth International Symposium on Intelligent Control Pub Date : 1995-08-27 DOI:10.1109/ISIC.1995.525058

D. Basch, M. Zagar

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引用次数: 2

摘要

本文描述了一种用于高速控制应用的模糊处理器的结构。它的主要优点是推理速度不依赖于使用的输入和规则的数量。这是通过使用内容可寻址内存作为规则集存储来实现的。对所提出的体系结构进行了仿真，仿真结果表明该体系的推理速度约为200 KFLIPS。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Processor architecture model for fuzzy control

In this paper, the architecture of a fuzzy processor intended for high-speed control applications is described. Its main advantage is the inference speed that does not depend on the number of used inputs and rules. This is accomplished by the usage of content addressable memory as a rule set storage. The proposed architecture was simulated and the simulation results give the inference speed of about 200 KFLIPS.

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Proceedings of Tenth International Symposium on Intelligent Control

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