Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic

This paper presents a novel bit-serial fine-grain pipelined reconfigurable VLSI architecture based on multiplexer logic to achieve high utilization of hardware resources and high throughput. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network. A multiplexer merged with a latch function is effectively employed for efficient fine-grain pipelined operation. A systematic mapping method for pipelined bit-serial operations is proposed using a data flow graph. As an extension of the reconfigurable VLSI based on the binary multiplexer logic, we introduce linear summation in the data transfer between logic blocks. A 4-valued multiplexer directly controlled by the linear sum can be effectively utilized to reduce complexity of the switch box.