利用新型睡眠晶体管技术设计d触发器

Ch. Meghana Reddy, Souvik Dhara, B. Srikanth, P. Ramakrishna
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引用次数: 2

摘要

d -触发器广泛应用于设计各种模拟、数字和混合信号。不同的移位寄存器,计数器和其他电路设计使用d -触发器。为了延长电池的使用时间并降低功耗,必须在待机模式下降低电路的电压。本文采用5晶体管D触发器、自电压电平D触发器、改进的SVL(自电压电平)D触发器和新型睡眠晶体管技术设计了不同的D触发器。对各设计方案在功率、延时、漏功率等方面进行了比较。所有的设计都是借助90nm技术的Cadence Virtuoso进行设计和仿真的。新型休眠晶体管技术的漏功率比改进的SVL技术低93.5%。
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Designing a D-Flipflop Using Novel Sleep Transistor Technique
D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique.
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