串扰免疫互连驱动设计

R. Weerasekera, Lirong Zheng, D. Pamunuwa, H. Tenhunen
{"title":"串扰免疫互连驱动设计","authors":"R. Weerasekera, Lirong Zheng, D. Pamunuwa, H. Tenhunen","doi":"10.1109/ISSOC.2004.1411168","DOIUrl":null,"url":null,"abstract":"The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit scheme called the crosstalk immune interconnect driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Crosstalk immune interconnect driver design\",\"authors\":\"R. Weerasekera, Lirong Zheng, D. Pamunuwa, H. Tenhunen\",\"doi\":\"10.1109/ISSOC.2004.1411168\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit scheme called the crosstalk immune interconnect driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.\",\"PeriodicalId\":268122,\"journal\":{\"name\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2004.1411168\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2004.1411168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

随着几何形状继续缩小到深亚微米范围,时钟频率增加到多GHz域,串扰噪声的影响变得越来越显著。相邻互连间耦合电容引起的动态延迟是静态时序分析中无法准确估计的关键问题。本文提出了一种新的驱动电路方案,称为串扰免疫互连驱动器(XTIID),用于电容耦合互连,消除了模式依赖的耦合噪声。此外,这种互连驱动技术有可能促进深亚微米VLSI设计中的动态时序问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Crosstalk immune interconnect driver design
The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit scheme called the crosstalk immune interconnect driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Design reuse and design for reuse, a case study on HDSL2 Development of NSoC program in Taiwan Efficient barrier synchronization mechanism for emulated shared memory NOCs Evaluation of platform architecture performance using abstract instruction-level workload models Assertion based verification of PSL for SystemC designs
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1