Hiroaki Inoue, K. Anjo, J. Yamamoto, J. Tanabe, Masaki Wakabayashi, M. Sato, H. Amano, K. Hiraki
{"title":"基于两种协议策略的大规模并行处理器jump -1 MBP-light的初步评估","authors":"Hiroaki Inoue, K. Anjo, J. Yamamoto, J. Tanabe, Masaki Wakabayashi, M. Sato, H. Amano, K. Hiraki","doi":"10.1109/FMPC.1999.750609","DOIUrl":null,"url":null,"abstract":"A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.","PeriodicalId":405655,"journal":{"name":"Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1\",\"authors\":\"Hiroaki Inoue, K. Anjo, J. Yamamoto, J. Tanabe, Masaki Wakabayashi, M. Sato, H. Amano, K. Hiraki\",\"doi\":\"10.1109/FMPC.1999.750609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.\",\"PeriodicalId\":405655,\"journal\":{\"name\":\"Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-02-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FMPC.1999.750609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1999.750609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
为了在超过1000个处理器的大型系统上构建高效的缓存相干分布式共享内存(DSM),开发了一种名为JUMP-1的大规模并行处理器。本文介绍了用于管理JUMP-1的DSM的专用处理器MBP (Memory Based processor)-light,并对其在更新/无效两种协议策略下的初步性能进行了评估。从仿真结果来看,标签检查和确认包的收集/生成等简单操作大多由硬件机制在MBP-light下处理,而无需核心处理器的帮助。此外,核心处理器在MBP-light中采用的缓冲寄存器架构被充分利用,可以处理两个策略的协议事务。
The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1
A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.