A novel dual-path architecture for HDTV video decoding

Summary form only given. We present an architecture for digital HDTV video decoding (MPEG-2 MP@HL), based on dual decoding data paths controlled in a block layer synchronization manner and an efficient write back scheme. Our fixed schedule controller synchronizes the baseline units on a block basis in both data-paths. This scheme reduces embedded buffer sizes within the decoder and eliminates a lot of external memory bus contentions. In our write back scheme, the display DRAM is physically separated from the anchor picture DRAM, and is added to the display engine, not to the bus. The slight increase in overall DRAM size is acceptable due to the low DRAM cost today. This improves the parallelism in accessing anchor and display pictures and saves about 80 clock cycles per macroblock (based on a 81 MHz clock). Compared to the other decoding approaches such as the slice bar decoding method and the crossing-divided method, this scheme reduces memory access contentions and the amount of embedded local memory required. Our simulations show that with a relatively low speed 81 MHz clock, our architecture uses fewer than the 332 cycles (required real-time decoding upper bound), to decode each macroblock, without a high cost in overall chip area.