具有100mhz采样和DCT频谱触发的第四代单FPGA前端板的原型用于俄歇表面探测器

Z. Szadkowski
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引用次数: 1

摘要

皮埃尔·奥格天文台的表面探测器阵列包含1600个水切伦科夫探测器,分布在3000平方公里的面积上。切伦科夫光由三个9英寸光电倍增管检测,其中阳极和最后一个阳极的信号由10位adc数字化。目前使用的配备ACEX®和Cyclone™芯片的几代前端板采用40 MHz时钟采样。来自Auger North (100 MHz)和AMIGA (80 MHz)规范的新要求以及基于16点离散余弦变换(DCT)的新频谱触发器的建议需要具有更强大的FPGA芯片的新前端板。DCT触发器只能在有足够数量的DSP块支持的较新的FPGA芯片中实现。DCT触发器允许识别ADC迹线,其上升时间非常短,指数衰减很快,这与强子产生的非常倾斜的广泛空气阵雨的窄而平坦的介子成分有关,并且在大气中开始早期发展。与基于复系数的离散傅立叶变换(DFT)相比,仅基于频域实系数的DCT提供了更敏感的触发条件和更简单的解释。它还提供了缩放功能。DCT系数与一阶谐波的比值只取决于信号的形状,而不取决于它们的振幅。在2009年4月19日至7月26日期间,已经制造了10个配备Altera®CycloneIII™FPGA的原型板,并在实验室和真实的潘巴斯条件下在六个测试表面探测器上进行了测试。主板只包含一个FPGA芯片,实现了前三代由外部双端口RAM支持的慢通道。经测试,数字部分完全稳定,可靠性高。实验室和现场测试都证实了对ADC走线的预期模式的高效率识别。
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The prototype of the 4th generation single FPGA Front-End Boards with 100 MHz sampling and DCT spectral trigger for Auger surface detectors
The surface detector array of the Pierre Auger Observatory contain 1600 water Cherenkov detectors spread over an area of 3000 km2. The Cherenkov light is detected by three 9-inch photomultiplier tubes from which the signals of the anode and last dynode are digitized by 10 bit ADCs. The currently used generations of the Front-End Boards equipped with the ACEX® and Cyclone™ chips were sampled with 40 MHz clock. New requirements from the Auger North (100 MHz) and AMIGA (80 MHz) specification as well as proposal of new spectral triggers based on the 16-point Discrete Cosine Transform (DCT) requires a new Front End Boards with more powerful FPGA chip. The DCT trigger can be only implemented in a newer FPGA chips supported by sufficient amount of DSP blocks. The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere. The DCT based on only real coefficients in the frequency domain, provides much more sensitive trigger conditions and a simpler interpretation in comparison to a discrete Fourier transform (DFT) that is based on complex coefficients. It also offers a scaling feature. The ratio of the DCT coefficients to the 1st harmonics depends only on the shape of signals, not on their amplitudes. 10 prototype boards equipped with Altera® CycloneIII™ FPGA have been fabricated and successively tested in the lab and in real pampas conditions in six test surface detectors within April 19 - July 26, 2009. Boards contain only a single FPGA chip, which implements also the slow channel, in previous three generations supported by the external Dual-Port RAM. Tests confirmed full stability and high reliability of the digital part. Both lab and field tests confirm a high efficiency of the recognition of expected patterns of ADC traces.
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Commissioning of the ATLAS High Level Trigger with proton collisions at the LHC Development of efficient FPGA-based phase meters for IR-interferometers. optimizations for multi-channel interferometers Real-time control of Extremely Large Telescope mirror systems using on-line high performance computing Developments for the PANDA online high level trigger Commissioning the trigger of the Compact Muon Solenoid experiment at the CERN Large Hadron Collider
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