{"title":"机载雷达信号处理器实现","authors":"Reena Mamgain, Rashi Jain","doi":"10.1109/WIECON-ECE.2017.8468930","DOIUrl":null,"url":null,"abstract":"Signal processor for airborne Active Electronically Scanned Array (AESA) radar has stringent requirement in terms of dynamic load handling, latency and throughput requirement. In this paper, Radar Signal Processor(RSP) realisation for airborne radar is discussed with specific emphasis on S/W architecture for its deployment on multiprocessor based H/W platform using Commercial Off The Shelf(COTS) board. The S/W architecture is based on master slave configuration which leverages parallelism. This architecture is termed as Cluster Of Processors(CoPs). Sizing analysis and benchmarking of computational resources is also done to ascertain the number of processors required to meet realtime performance. In addition to it, a case study for RSP is also carried to outline the realisation of optimised RSP.","PeriodicalId":188031,"journal":{"name":"2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Airborne Radar Signal Processor Realisation\",\"authors\":\"Reena Mamgain, Rashi Jain\",\"doi\":\"10.1109/WIECON-ECE.2017.8468930\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Signal processor for airborne Active Electronically Scanned Array (AESA) radar has stringent requirement in terms of dynamic load handling, latency and throughput requirement. In this paper, Radar Signal Processor(RSP) realisation for airborne radar is discussed with specific emphasis on S/W architecture for its deployment on multiprocessor based H/W platform using Commercial Off The Shelf(COTS) board. The S/W architecture is based on master slave configuration which leverages parallelism. This architecture is termed as Cluster Of Processors(CoPs). Sizing analysis and benchmarking of computational resources is also done to ascertain the number of processors required to meet realtime performance. In addition to it, a case study for RSP is also carried to outline the realisation of optimised RSP.\",\"PeriodicalId\":188031,\"journal\":{\"name\":\"2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WIECON-ECE.2017.8468930\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WIECON-ECE.2017.8468930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Signal processor for airborne Active Electronically Scanned Array (AESA) radar has stringent requirement in terms of dynamic load handling, latency and throughput requirement. In this paper, Radar Signal Processor(RSP) realisation for airborne radar is discussed with specific emphasis on S/W architecture for its deployment on multiprocessor based H/W platform using Commercial Off The Shelf(COTS) board. The S/W architecture is based on master slave configuration which leverages parallelism. This architecture is termed as Cluster Of Processors(CoPs). Sizing analysis and benchmarking of computational resources is also done to ascertain the number of processors required to meet realtime performance. In addition to it, a case study for RSP is also carried to outline the realisation of optimised RSP.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
