Timing consideration in synchronous system level design

This paper describes the architecture of system level design for the analysis of fiber parameters for one simulation step considering the synchronous and timing issues. The challenge in realizing these systems is not only the hardware but also complex control design that marshals the data flow. In a well-thought-out system level design approach it is necessary in splitting the design into several sub-modules, each addressing the specific timing and synchronizing issues. For the split step Fourier algorithm a system level model is designed considering the data path and control architecture. The timing and synchronizing are considering in RTL validation using Xilinx device XC5VLX30TFF655 with speed grade −3.