基于FPGA的二维和三维cnn加速统一模板架构研究

Junzhong Shen, Y. Huang, Zelong Wang, Yuran Qiao, M. Wen, Chunyuan Zhang
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引用次数: 80

摘要

三维卷积神经网络(3D cnn)在许多计算机视觉应用中得到了有效的应用。在这一领域的大多数工作只集中在设计和优化2D CNN的加速器上,很少尝试在FPGA上加速3D CNN。我们发现在FPGA上加速3D cnn由于其高计算复杂度和存储需求是一个挑战。更重要的是,尽管2D和3D CNN的计算模式是相似的,但传统的加速2D CNN的方法可能不适用于3D CNN的加速。为了使用统一的框架加速2D和3D CNN,本文提出了一种统一的基于模板的架构,该架构使用基于Winograd算法的模板来保证2D和3D CNN加速器的快速开发。此外,我们还开发了一个统一的分析模型,以促进基于我们的架构的二维和三维CNN加速器的有效设计空间探索。最后,我们通过在多个FPGA平台上为现实生活中的2D和3D cnn (VGG16和C3D)实现加速器来证明基于模板的架构的有效性。在S2C VUS440上,VGG16和C3D在低资源利用率下分别达到1.13 TOPS和1.11 TOPS。与CPU和GPU解决方案的端到端比较表明,与CPU解决方案相比,我们的C3D实现了高达13倍和60倍的性能和能量增益,并且比GPU解决方案获得了6.4倍的能效增益。
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Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA
Three-dimensional convolutional neural networks (3D CNNs) are used efficiently in many computer vision applications. Most previous work in this area has concentrated only on designing and optimizing accelerators for 2D CNN, with few attempts made to accelerate 3D CNN on FPGA. We find accelerating 3D CNNs on FPGA to be challenge due to their high computational complexity and storage demands. More importantly, although the computation patterns of 2D and 3D CNNs are analogous, the conventional approaches adopted for accelerating 2D CNNs may be unfit for 3D CNN acceleration. In this paper, in order to accelerate 2D and 3D CNNs using a uniform framework, we propose a uniform template-based architecture that uses templates based on the Winograd algorithm to ensure fast development of 2D and 3D CNN accelerators. Furthermore, we also develop a uniform analytical model to facilitate efficient design space explorations of 2D and 3D CNN accelerators based on our architecture. Finally, we demonstrate the effectiveness of the template-based architecture by implementing accelerators for real-life 2D and 3D CNNs (VGG16 and C3D) on multiple FPGA platforms. On S2C VUS440, we achieve up to 1.13 TOPS and 1.11 TOPS under low resource utilization for VGG16 and C3D, respectively. End-to-end comparisons with CPU and GPU solutions demonstrate that our implementation of C3D achieves gains of up to 13x and 60x in performance and energy relative to a CPU solution, and a 6.4x energy efficiency gain over a GPU solution.
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Architecture and Circuit Design of an All-Spintronic FPGA Session details: Session 6: High Level Synthesis 2 A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only) Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only) Session details: Special Session: Deep Learning
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