Low-power design technique with ambipolar double gate devices

Ambipolar FETs with channels composed of carbon nanotubes, graphene or undoped silicon nanowires have a Vds-dependent Ioff, a source of high leakage, as well as a low VTH, a source of high dynamic power. In this paper, we propose a circuit design technique to solve these issues for low-power logic circuits with ambipolar double-gate transistors, using the in-field controllability via the fourth device terminal. The approach is demonstrated for the complementary static logic design style. It dynamically lowers the dynamic power (short-circuit and capacitive) during the active mode and the static power during the inactive mode. We apply this approach in a simulation-based case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Compared to conventional structures, an average improvement of 3X in total power consumption was observed, with a decrease by a factor of 4X in short circuit power, and of 100X in static power (during the standby mode).