验证方法，以保证较低的走线阻力

2018 19th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2018-03-01 DOI:10.1109/ISQED.2018.8357297

M. Fakhruddin, Kuok-Khian Lo, J. Karp, M. Hart, Min-Hsing P. Chen

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引用次数: 0

摘要

所提出的验证方法使设计人员能够满足井口走向的最大阻力规范。该流的主要优势是:自动识别井的抽头和VDD/VSS网格;将所提取的电阻与用户定义的规格值进行比较;用图形界面审查结果;没有标记层来识别提取路径。

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Verification methodology to guarantee low routing resistance to well taps

The proposed verification methodology enables designers to meet a maximum resistance specification for the well taps routing. Key strengths of the flow are: automatic identification of both well taps and VDD/VSS grid; comparison of the extracted resistance to a user defined specification value; review of results with a graphical interface; no marker layers to identify the extraction path.

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2018 19th International Symposium on Quality Electronic Design (ISQED)

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